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Sac State - FALL 2012 | ||
Section 01 | ||
SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling (2nd Edition) by Stuart Sutherland, Simon Davidmann, Peter Flake, P. Moorby (Foreword), Phil Moorby Hardcover, 418 Pages, Published 2006 ISBN-10: 0-387-33399-1 / 0387333991 ISBN-13: 978-0-387-33399-1 / 9780387333991 SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL-based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs |