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 | | System-on-a-Chip Verification - Methodology and Techniques by Prakash Rashinkar, Peter Paterson, Leena Singh ISBN-10: 9780792372790 ISBN-10: 0-7923-7279-4 ISBN-13: 9780792372790 ISBN-13: 978-0-7923-7279-0 Hardcover 2000-12-31 Springer Find Lowest Price |
Editorials | ||
Product Description System-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for Bluetooth application. System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter:
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Reviews | ||
A first attempt at digital system on a chip verification. I was excited to find this book because of these quotations from the book's back cover: "[fully covers] system on a chip," "Bluetooth because it addresses reality," "comprehensive guide to overall SOC verification," and "authors... leave no stone unturned in this comprehensive overview of [chip verification] tools and methodologies." "Analog engineers have been using [SPICE] for analog simulation for over 30 years..." Given the above comments, I had hoped that it had some analog verification info. It turns out to have no significant coverage of analog. And even the digital system on a chip verification coverage seems rushed. I am an analog chip designer that has 24 years experience, a good part of that time spent verifying my analog and mixed-signal designs. This book has a single 24 page chapter on analog, "Analog/Mixed-Signal Simulation," which taught me nothing. The chapter lists and defines the standard specialized nomenclature of the analog verification software, gives an example simple VerilogA behavioral model for a crude resistor-transresistor DAC, and gives a crude behavioral test example. I think that most all stones are left unturned for analog or mixed-signal chip verification. The authors mention SPICE, spectre, and Cadence Analog Design Environment only. I just finished a 37000 transistor analog & mixed-signal chip verification, and this book mentioned none of the tools and methods that I used, which included Mentor's Modeltech Modelsim and Synopsys's Saber, digital and analog coupled together. The examples are of value in giving existing digital chip verification experts an example of how to get started with a crude VerilogA behavioural modeling of analog blocks to be fit into a digital chip verification flow. I thank the authors for their book in this area with little publisher coverage. | ||
Poor examples explanation I am not an expert in this field but what I learn are just some simple concepts. It takes some pages on the bluetooth SOC design example with fractional C code. There is no structure about the examples and its hard to understand what the authors will explain(actually, I just feel ??what??) | ||