Principles of Verifiable RTL Design Second Edition - A Functional Coding Style Supporting Verification Processes in Verilog by Lionel Bening - 9780792373681 - Compare Discount Book Prices & Save up to 90%

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		Principles of Verifiable RTL Design Second Edition - A Functional Coding Style Supporting Verification Processes in Verilog by Lionel Bening, Harry D. Foster ISBN-10: 9780792373681 ISBN-10: 0-7923-7368-5 ISBN-13: 9780792373681 ISBN-13: 978-0-7923-7368-1 Hardcover 2001-05-01 Springer Find Lowest Price
Editorials

Product Description The first edition of Principles of Verifiable RTL Design offered a common sense method for simplifying and unifying assertion specification by creating a set of predefined specification modules that could be instantiated within the designer's RTL. Since the release of the first edition, an entire industry-wide initiative for assertion specification has emerged based on ideas presented in the first edition. This initiative, known as the Open Verification Library Initiative (www.verificationlib.org), provides an assertion interface standard that enables the design engineer to capture many interesting properties of the design and precludes the need to introduce new HDL constructs (i.e., extensions to Verilog are not required). Furthermore, this standard enables the design engineer to `specify once,' then target the same RTL assertion specification over multiple verification processes, such as traditional simulation, semi-formal and formal verification tools. The Open Verification Library Initiative is an empowering technology that will benefit design and verification engineers while providing unity to the EDA community (e.g., providers of testbench generation tools, traditional simulators, commercial assertion checking support tools, symbolic simulation, and semi-formal and formal verification tools). The second edition of Principles of Verifiable RTL Design expands the discussion of assertion specification by including a new chapter entitled `Coverage, Events and Assertions'. All assertions exampled are aligned with the Open Verification Library Initiative proposed standard. Furthermore, the second edition provides expanded discussions on the following topics: start-up verification; the place for 4-state simulation; race conditions; RTL-style-synthesizable RTL (unambiguous mapping to gates); more `bad stuff'. The goal of the second edition is to keep the topic current. Principles of Verifiable RTL Design, A Functional Coding Style Supporting Verification Processes, Second Edition tells you how you can write Verilog to describe chip designs at the RTL level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process.
Reviews

has practical tips, is shallow in giving understanding The chapter on bad stuff is useful and practical, even though it repeats parts of previous chapters. The chapter on assertion based verification is practical too. Some of the reasonings on use of "x" may be debatable. For example, the authors argued that two-state detects more problems than x injection, based on their experiences. In the text, an example was given. What the example illustrates is NOT the inherent problems with x injection but a truly bad style of coding to detect x. Thus, the example is misleading. The chapter on formal verification is a cheat-sheet user manual for some commercial tools. It gives a couple of lines of math symbols about formal verification theory, without explanation whatsoever. In general, this chapter is too shallow for understanding the ideas behind formal verification. In many places, the book just lists the benefits of some practices without giving reasons and details about the practices. It's very frustrating to have the thought hung in mid-air. So if you are looking for a partial collection of tips to avoid simulation based verification problems, this book is a start. If you want a more in-depth and complete understanding in verifiable RTL design, find other books.
An excellent book for advanced users This book presents principles drawn from very large scale designs, like microprocessor. If you are looking for a book describing testbench implementation, another book, "Writing testbenches functional verification of hdl models", is more suitable. If you are working on very large scale and complex design verification, this book will be very helpful. The discussion of simulation optimization, X/Z state, X/Zero/Random initialization during simulation is very insightful.
Out of the ordinary If you are looking for another book describing the Verilog Language Reference Manual then this book is not for you. If, however, to are looking for an excellent set of principles to build a design and verification philosophy then I highly recommend this book. The authors have produced an RTL centric view of design emphasizing the verification process. They argue that synthesis productivity gains have now placed the verification process in the critical path and that equal attention should be giving to coding for verification as is currently given to coding for synthesis. The chapter I particularly enjoyed, entitled "Bad Stuff," provides an excellent discussion with examples on coding styles that hinder efficient verification. The author's discussion of the problems with the use of X at the RT-level, due to X-state pessimism and optimism, and the need for 2-state RTL simulation is enlightening.

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